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19-5225; Rev 0; 4/10
KIT ATION EVALU BLE AVAILA
2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 1-/2-Channel, 2-Wire Serial, 12-Bit ADCs
General Description
The MAX11644/MAX11645 low-power, 12-bit, 1-/2channel analog-to-digital converters (ADCs) feature internal track/hold (T/H), voltage reference, clock, and an I2C-compatible 2-wire serial interface. These devices operate from a single supply of 2.7V to 3.6V (MAX11645) or 4.5V to 5.5V (MAX11644) and require only 670A at the maximum sampling rate of 94.4ksps. Supply current falls below 230A for sampling rates under 40ksps. AutoShutdownTM powers down the devices between conversions, reducing supply current to less than 1A at low throughput rates. The MAX11644/MAX11645 each measure two single-ended or one differential input. The fully differential analog inputs are software configurable for unipolar or bipolar, and single-ended or differential operation. The full-scale analog input range is determined by the internal reference or by an externally applied reference voltage ranging from 1V to VDD. The MAX11645 features a 2.048V internal reference and the MAX11644 features a 4.096V internal reference. The MAX11644/MAX11645 are available in an 8-pin MAX(R) package. The MAX11644/MAX11645 are guaranteed over the extended temperature range (-40C to +85C). For pin-compatible 10-bit parts, refer to the MAX11646/MAX11647 data sheet.
Features
o High-Speed I2C-Compatible Serial Interface 400kHz Fast Mode 1.7MHz High-Speed Mode Single-Supply 2.7V to 3.6V (MAX11645) 4.5V to 5.5V (MAX11644) Internal Reference 2.048V (MAX11645) 4.096V (MAX11644) External Reference: 1V to VDD Internal Clock 2-Channel Single-Ended or 1-Channel Fully Differential Internal FIFO with Channel-Scan Mode Low Power 670A at 94.4ksps 230A at 40ksps 60A at 10ksps 6A at 1ksps 0.5A in Power-Down Mode Software-Configurable Unipolar/Bipolar Small, 8-Pin MAX Package
MAX11644/MAX11645
o
o
o o
o o
o o
Applications
Handheld Portable Applications Medical Instruments Battery-Powered Test Equipment Solar-Powered Remote Systems Received-Signal-Strength Indicators System Supervision Power-Supply Monitoring
MAX11644EUA+ MAX11645EUA+ -40C to +85C -40C to +85C PART
Ordering Information
TEMP RANGE PINPACKAGE 8 MAX 8 MAX I2C SLAVE ADDRESS 0110110 0110110
+Denotes a lead(Pb)-free/RoHs-compliant package.
Typical Operating Circuit and Selector Guide appear at end of data sheet.
AutoShutdown is a trademark and MAX is a registered trademark of Maxim Integrated Products, Inc.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/12-Channel, 2-Wire Serial, 12-Bit ADCs MAX11644/MAX11645
ABSOLUTE MAXIMUM RATINGS
VDD to GND ..............................................................-0.3V to +6V AIN0, AIN1, REF to GND ..............................-0.3V to the lower of (VDD + 0.3V) and 6V SDA, SCL to GND.....................................................-0.3V to +6V Maximum Current into Any Pin .........................................50mA Continuous Power Dissipation (TA = +70C) 8-Pin MAX (derate 4.5mW/C above +70C) ..............362mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-60C to +150C Lead Temperature (soldering, 10s) .................................+300C Soldering Temperature (reflow) .......................................+260C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = 2.7V to 3.6V (MAX11645), VDD = 4.5V to 5.5V (MAX11644), VREF = 2.048V (MAX11645), VREF = 4.096V (MAX11644), fSCL = 1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C, see Tables 1-5 for programming notation.)
PARAMETER DC ACCURACY (Note 1) Resolution Relative Accuracy Differential Nonlinearity Offset Error Offset-Error Temperature Coefficient Gain Error Gain-Temperature Coefficient Channel-to-Channel Offset Matching Channel-to-Channel Gain Matching DYNAMIC PERFORMANCE (fIN(SINE-WAVE) = 10kHz, VIN(P-P) = VREF, fSAMPLE = 94.4ksps) Signal-to-Noise Plus Distortion Total Harmonic Distortion Spurious-Free Dynamic Range Full-Power Bandwidth Full-Linear Bandwidth CONVERSION RATE Conversion Time (Note 4) Throughput Rate Track/Hold Acquisition Time Internal Clock Frequency Aperture Delay (Note 5) tAD External clock, fast mode External clock, high-speed mode tCONV fSAMPLE Internal clock External clock Internal clock, SCAN[1:0] = 01 External clock 800 2.8 60 30 10.6 51 94.4 7.5 s ksps ns MHz ns SINAD THD SFDR SINAD > 68dB -3dB point Up to the 5th harmonic 70 -78 78 3 5 dB dB dB MHz MHz Relative to FSR (Note 3) Relative to FSR 0.3 0.1 0.1 0.3 4 INL DNL (Note 2) No missing codes over temperature 12 1 1 4 Bits LSB LSB LSB ppm/C LSB ppm/C LSB LSB SYMBOL CONDITIONS MIN TYP MAX UNITS
2
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2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 1-/2-Channel, 2-Wire Serial, 12-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 3.6V (MAX11645), VDD = 4.5V to 5.5V (MAX11644), VREF = 2.048V (MAX11645), VREF = 4.096V (MAX11644), fSCL = 1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C, see Tables 1-5 for programming notation.)
PARAMETER ANALOG INPUT (AIN0/AIN1) Input Voltage Range, SingleEnded and Differential (Note 6) Input Multiplexer Leakage Current Input Capacitance INTERNAL REFERENCE (Note 7) Reference Voltage Reference-Voltage Temperature Coefficient REF Short-Circuit Current REF Source Impedance EXTERNAL REFERENCE REF Input Voltage Range REF Input Current Input-High Voltage Input-Low Voltage Input Hysteresis Input Current Input Capacitance Output Low Voltage POWER REQUIREMENTS Supply Voltage VDD MAX11645 MAX11644 fSAMPLE = 94.4ksps external clock fSAMPLE = 40ksps internal clock Supply Current IDD fSAMPLE = 10ksps internal clock fSAMPLE =1ksps internal clock Power-Supply Rejection Ratio PSRR Internal reference External reference Internal reference External reference Internal reference External reference Internal reference External reference 2.7 4.5 900 670 530 230 380 60 330 6 0.5 0.5 10 2.0 LSB/V A 3.6 5.5 1150 900 V VREF IREF VIH VIL VHYST IIN CIN VOL ISINK = 3mA VIN = 0 to VDD 15 0.4 0.1 x VDD 10 (Note 8) fSAMPLE = 94.4ksps 0.7 x VDD 0.3 x VDD 1 VDD 40 V A V V V A pF V 1.5 VREF TCVREF TA = +25C MAX11645 MAX11644 1.968 3.936 2.048 4.096 25 2 2.128 4.256 V ppm/C mA k CIN Unipolar Bipolar On/off leakage current, VAIN_ = 0 or VDD 0 0 0.01 22 VREF VREF/2 1 V A pF SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX11644/MAX11645
DIGITAL INPUTS/OUTPUTS (SCL, SDA)
Shutdown (internal REF off) Full-scale input (Note 9)
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2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 1-/2-Channel, 2-Wire Serial, 12-Bit ADCs MAX11644/MAX11645
TIMING CHARACTERISTICS (Figure 1)
(VDD = 2.7V to 3.6V (MAX11645), VDD = 4.5V to 5.5V (MAX11644), VREF = 2.048V (MAX11645), VREF = 4.096V (MAX11644), fSCL = 1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C, see Tables 1-5 for programming notation.)
PARAMETER Serial-Clock Frequency Bus Free Time Between a STOP (P) and a START (S) Condition Hold Time for START Condition Low Period of the SCL Clock High Period of the SCL Clock Setup Time for a Repeated START (Sr) Condition Data Hold Time Data Setup Time Rise Time of Both SDA and SCL Signals, Receiving Fall Time of SDA Transmitting Setup Time for STOP Condition Capacitive Load for Each Bus Line Pulse Width of Spike Suppressed Serial-Clock Frequency Hold Time, Repeated START Condition Low Period of the SCL Clock High Period of the SCL Clock Setup Time for a Repeated START Condition Data Hold Time Data Setup Time Rise Time of SCL Signal (Current Source Enabled) SYMBOL fSCL tBUF tHD,STA tLOW tHIGH tSU,STA tHD,DAT tSU,DAT tR tF tSU,STO CB tSP fSCLH tHD,STA tLOW tHIGH tSU,STA tHD,DAT tSU,DAT tRCL (Note 10) (Note 13) 160 320 120 160 0 10 20 80 150 Measured from 0.3VDD - 0.7VDD Measured from 0.3VDD - 0.7VDD (Note 11) (Note 10) 1.3 0.6 1.3 0.6 0.6 0 100 20 + 0.1CB 20 + 0.1CB 0.6 400 50 1.7 300 300 900 CONDITIONS MIN TYP MAX 400 UNITS kHz s s s s s ns ns ns ns s pF ns MHz ns ns ns ns ns ns ns
TIMING CHARACTERISTICS FOR FAST MODE
TIMING CHARACTERISTICS FOR HIGH-SPEED MODE (CB = 400pF, Note 12)
4
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2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 1-/2-Channel, 2-Wire Serial, 12-Bit ADCs
TIMING CHARACTERISTICS (Figure 1) (continued)
(VDD = 2.7V to 3.6V (MAX11645), VDD = 4.5V to 5.5V (MAX11644), VREF = 2.048V (MAX11645), VREF = 4.096V (MAX11644), fSCL = 1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C, see Tables 1-5 for programming notation.)
PARAMETER Rise Time of SCL Signal After Acknowledge Bit Fall Time of SCL Signal Rise Time of SDA Signal Fall Time of SDA Signal Setup Time for STOP Condition Capacitive Load for Each Bus Line Pulse Width of Spike Suppressed SYMBOL tRCL1 tFCL tRDA tFDA tSU, STO CB tSP (Notes 10 and 13) 0 CONDITIONS Measured from 0.3VDD - 0.7VDD Measured from 0.3VDD - 0.7VDD Measured from 0.3VDD - 0.7VDD Measured from 0.3VDD - 0.7VDD (Note 11) MIN 20 20 20 20 160 400 10 TYP MAX 160 80 160 160 UNITS ns ns ns ns ns pF ns
MAX11644/MAX11645
Note 1: For DC accuracy, the MAX11644 is tested at VDD = 5V and the MAX11645 is tested at VDD = 3V with an external reference for both ADCs. All devices are configured for unipolar, single-ended inputs. Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and offsets have been calibrated. Note 3: Offset nulled. Note 4: Conversion time is defined as the number of clock cycles needed for conversion multiplied by the clock period. Conversion time does not include acquisition time. SCL is the conversion clock in the external clock mode. Note 5: A filter on the SDA and SCL inputs suppresses noise spikes and delays the sampling instant. Note 6: The absolute input voltage range for the analog inputs (AIN0/AIN1) is from GND to VDD. Note 7: When the internal reference is configured to be available at REF (SEL[2:1] = 11), decouple REF to GND with a 0.1F capacitor and a 2k series resistor (see the Typical Operating Circuit). Note 8: ADC performance is limited by the converter's noise floor, typically 300VP-P. Note 9: Measured for the MAX11645 as:
2N VFS (3.6V) - VFS (2.7V) x V REF (3.6V - 2.7V)
and for the MAX11644, where N is the number of bits:
2N VFS (5.5V) - VFS (4.5V) x V REF (5.5V - 4.5V)
Note 10: A master device must provide a data hold time for SDA (referred to VIL of SCL) to bridge the undefined region of SCL's falling edge (see Figure 1). Note 11: The minimum value is specified at TA = +25C. Note 12: CB = total capacitance of one bus line in pF. Note 13: fSCL must meet the minimum clock low time plus the rise/fall times.
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2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 1-/2-Channel, 2-Wire Serial, 12-Bit ADCs MAX11644/MAX11645
Typical Operating Characteristics
(VDD = 3.3V (MAX11645), VDD = 5V (MAX11644), fSCL = 1.7MHz, 50% duty cycle, fSAMPLE = 94.4ksps, single-ended, unipolar, TA = +25C, unless otherwise noted.)
DIFFERENTIAL NONLINEARITY vs. DIGITAL CODE
MAX11644 toc01
INTEGRAL NONLINEARITY vs. DIGITAL CODE
MAX11644 toc02
FFT PLOT
fSAMPLE = 94.4ksps fIN = 10kHz
MAX11644 toc03
0.5 0.4 0.3 0.2 DNL (LSB) 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0
1.0 0.8 0.6 0.4 INL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0
-20 -40 AMPLITUDE (dBc) -60 -80 -100 -120
500 1000 1500 2000 2500 3000 3500 4000 DIGITAL OUTPUT CODE
0
500 1000 1500 2000 2500 3000 3500 4000 DIGITAL OUTPUT CODE
-140 0 10k 20k 30k 40k 50k FREQUENCY (Hz)
SUPPLY CURRENT vs. TEMPERATURE
750 700 SUPPLY CURRENT (A) 650 600 550 500 450 400 350 300 -40 -25 -10 5 20 35 50 65 80 TEMPERATURE (C) EXTERNAL REFERENCE MAX11645 0 2.7 EXTERNAL REFERENCE MAX11644 0.2 0.1 INTERNAL REFERENCE MAX11645 INTERNAL REFERENCE MAX11644 SETUP BYTE EXT REF: 10111011 INT REF: 11011011
MAX11644 toc04
SHUTDOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE
SDA = SCL = VDD 0.5 0.4 IDD (A) 0.3
MAX11644 toc05
800
0.6
3.2
3.7
4.2
4.7
5.2
SUPPLY VOLTAGE (V)
SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE
MAX11644 toc06
ANALOG SUPPLY CURRENT vs. CONVERSION RATE (EXTERNAL CLOCK)
900 800 AVERAGE IDD (A) 700 600 500 400 300 200 100 0 EXTERNAL REFERENCE INTERNAL REFERENCE ALWAYS ON
MAX11644 toc07
0.50 0.45 0.40 SUPPLY CURRENT (A) 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 -40 -25 -10 5 20 35 50 65 80 TEMPERATURE (C) MAX11645 MAX11644
1000
0
20
40
60
80
100
CONVERSION RATE (ksps)
6
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2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 1-/2-Channel, 2-Wire Serial, 12-Bit ADCs
Typical Operating Characteristics (continued)
(VDD = 3.3V (MAX11645), VDD = 5V (MAX11644), fSCL = 1.7MHz, 50% duty cycle, fSAMPLE = 94.4ksps, single-ended, unipolar, TA = +25C, unless otherwise noted.)
INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE
1.0008 1.0006 VREF NORMALIZED 1.0004 VREF (V) 1.0002 1.0000 0.9998 0.9996 0.9994 0.9992 0.9990 -40 -25 -10 5 20 35 50 65 80 TEMPERATURE (C) MAX11645 NORMALIZED TO VALUE AT TA = +25C MAX11644
MAX11644 toc09
MAX11644/MAX11645
NORMALIZED REFERENCE VOLTAGE vs. SUPPLY VOLTAGE
1.00008 1.00006 1.00004 1.00002 1.00000 0.99998 0.99996 0.99994 0.99992 0.99990 MAX11645 NORMALIZED TO REFERENCE VALUE AT VDD = 3.3V 2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 VDD (V) MAX11644 NORMALIZED TO REFERENCE VALUE AT VDD = 5V
MAX11644 toc10
1.0010
1.00010
OFFSET ERROR vs. TEMPERATURE
MAX11644 toc11
OFFSET ERROR vs. SUPPLY VOLTAGE
1.6 1.2 OFFSET ERROR (LSB) 0.8 0.4 0 -0.4 -0.8 -1.2 -1.6 -2.0
MAX11644 toc12
0 -0.1 -0.2 OFFSET ERROR (LSB) -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 -1.0 -40 -25 -10 5 20 35 50 65 80 TEMPERATURE (C)
2.0
2.7
3.2
3.7
4.2 VDD (V)
4.7
5.2 5.5
GAIN ERROR vs. TEMPERATURE
MAX11644 toc13
GAIN ERROR vs. SUPPLY VOLTAGE
1.6 1.2 GAIN ERROR (LSB) 0.8 0.4 0 -0.4 -0.8 -1.2 -1.6 -2.0
MAX11644 toc14
2.0 1.8 1.6 GAIN ERROR (LSB) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 -40 -25 -10 5 20 35 50 65 80 TEMPERATURE (C)
2.0
2.7
3.2
3.7
4.2 VDD (V)
4.7
5.2 5.5
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2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 1-/2-Channel, 2-Wire Serial, 12-Bit ADCs MAX11644/MAX11645
Pin Configuration
TOP VIEW +
AIN0 1 AIN1 2 N.C. 3 8 7 VDD GND SDA SCL
MAX11644 MAX11645
6 5
REF 4
MAX
Pin Description
PIN 1, 2 3 4 5 6 7 8 NAME AIN0, AIN1 N.C. REF SCL SDA GND VDD Analog Inputs No Connection. Not internally connected. Reference Input/Output. Selected in the setup register (see Tables 1 and 6). Clock Input Data Input/Output Ground Positive Supply. Bypass to GND with a 0.1F capacitor. FUNCTION
A) F/S-MODE 2-WIRE SERIAL-INTERFACE TIMING
tR
tF
t
SDA
tSU,DAT tLOW
tHD,DAT tSU,STA
tHD,STA tSU,STO
tBUF
SCL
tHD,STA tR S B) HS-MODE 2-WIRE SERIAL-INTERFACE TIMING
tHIGH tF Sr A tRDA P S tFDA
SDA
tSU,DAT tLOW
tHD,DAT tSU,STA
tHD,STA
tBUF tSU,STO
SCL
tHD,STA tRCL S
tHIGH tFCL Sr HS MODE A tRCL1 P S F/S MODE
Figure 1. 2-Wire Serial-Interface Timing
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2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 1-/2-Channel, 2-Wire Serial, 12-Bit ADCs MAX11644/MAX11645
SDA SCL INPUT SHIFT REGISTER VDD SETUP REGISTER GND CONFIGURATION REGISTER CONTROL LOGIC INTERNAL OSCILLATOR
AIN0 AIN1 T/H 12-BIT ADC
OUTPUT SHIFT REGISTER AND RAM
ANALOG INPUT MUX
REF
REFERENCE 4.096V (MAX11644) 2.048V (MAX11645) REF
MAX11644 MAX11645
Figure 2. Simplified Functional Diagram
VDD IOL
serial interface supporting data rates up to 1.7MHz. Figure 2 shows the simplified internal structure for the MAX11644/MAX11645.
Power Supply
SDA VOUT 400pF IOH
The MAX11644/MAX11645 operate from a single supply and consume 670A (typ) at sampling rates up to 94.4ksps. The MAX11645 feature a 2.048V internal reference and the MAX11644 feature a 4.096V internal reference. All devices can be configured for use with an external reference from 1V to VDD.
Analog Input and Track/Hold
Figure 3. Load Circuit
Detailed Description
The MAX11644/MAX11645 analog-to-digital converters (ADCs) use successive-approximation conversion techniques and fully differential input track/hold (T/H) circuitry to capture and convert an analog signal to a serial 12-bit digital output. The MAX11644/MAX11645 measure either two single-ended or one differential input(s). These devices feature a high-speed, 2-wire
The MAX11644/MAX11645 analog-input architecture contains an analog-input multiplexer (mux), a fully differential track-and-hold (T/H) capacitor, T/H switches, a comparator, and a fully differential switched capacitive digital-to-analog converter (DAC) (Figure 4). In single-ended mode, the analog input multiplexer connects CT/H between the analog input selected by CS[0] (see the Configuration/Setup Bytes (Write Cycle) section) and GND (Table 3). In differential mode, the analog-input multiplexer connects CT/H to the + and analog inputs selected by CS[0] (Table 4).
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2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 1-/2-Channel, 2-Wire Serial, 12-Bit ADCs MAX11644/MAX11645
During the acquisition interval, the T/H switches are in the track position and CT/H charges to the analog input signal. At the end of the acquisition interval, the T/H switches move to the hold position retaining the charge on CT/H as a stable sample of the input signal. During the conversion interval, the switched capacitive DAC adjusts to restore the comparator input voltage to 0V within the limits of a 12-bit resolution. This action requires 12 conversion clock cycles and is equivalent to transferring a charge of 11pF x (VIN+ - VIN-) from CT/H to the binary weighted capacitive DAC, forming a digital representation of the analog input signal. Sufficiently low source impedance is required to ensure an accurate sample. A source impedance of up to 1.5k does not significantly degrade sampling accuracy. To minimize sampling errors with higher source impedances, connect a 100pF capacitor from the analog input to GND. This input capacitor forms an RC filter with the source impedance limiting the analog-input bandwidth. For larger source impedances, use a buffer amplifier to maintain analog-input signal integrity and bandwidth. When operating in internal clock mode, the T/H circuitry enters its tracking mode on the eighth rising clock edge of the address byte. See the Slave Address section. The T/H circuitry enters hold mode on the falling clock edge of the acknowledge bit of the address byte (the ninth clock pulse). A conversion or a series of conversions is then internally clocked and the MAX11644/ MAX11645 hold SCL low. With external clock mode, the T/H circuitry enters track mode after a valid address on the rising edge of the clock during the read (R/W = 1) bit. Hold mode is then entered on the rising edge of the second clock pulse during the shifting out of the first byte of the result. The conversion is performed during the next 12 clock cycles. The time required for the T/H circuitry to acquire an input signal is a function of the input sample capacitance. If the analog-input source impedance is high, the acquisition time constant lengthens and more time must be allowed between conversions. The acquisition time (tACQ) is the minimum time needed for the signal to be acquired. It is calculated by: tACQ 95 (RSOURCE + RIN) x CIN where RSOURCE is the analog-input source impedance, RIN = 2.5k, and CIN = 22pF. tACQ is 1.5/fSCL for internal clock mode and tACQ = 2/fSCL for external clock mode.
Analog Input Bandwidth
The MAX11644/MAX11645 feature input-tracking circuitry with a 5MHz small-signal bandwidth. The 5MHz input bandwidth makes it possible to digitize highspeed transient events and measure periodic signals with bandwidths exceeding the ADC's sampling rate by using under sampling techniques. To avoid high-frequency signals being aliased into the frequency band of interest, anti-alias filtering is recommended.
REF ANALOG INPUT MUX AIN0
HOLD
CT/H CAPACITIVE DAC
TRACK
AIN1
HOLD
TRACK
VDD/2
TRACK HOLD
TRACK
GND CT/H
TRACK
HOLD
CAPACITIVE DAC
HOLD
REF MAX11644 MAX11645
Figure 4. Equivalent Input Circuit
10
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2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 1-/2-Channel, 2-Wire Serial, 12-Bit ADCs
Analog Input Range and Protection
Internal protection diodes clamp the analog input to VDD and GND. These diodes allow the analog inputs to swing from (GND - 0.3V) to (VDD + 0.3V) without causing damage to the device. For accurate conversions, the inputs must not go more than 50mV below GND or above VDD. The data on SDA must remain stable during the high period of the SCL clock pulse. Changes in SDA while SCL is stable are considered control signals (see the START and STOP Conditions section). Both SDA and SCL remain high when the bus is not busy.
MAX11644/MAX11645
Single-Ended/Differential Input
The SGL/DIF of the configuration byte configures the MAX11644/MAX11645 analog-input circuitry for singleended or differential inputs (Table 2). In single-ended mode (SGL/DIF = 1), the digital conversion results are the difference between the analog input selected by CS[0] and GND (Table 3). In differential mode (SGL/ DIF = 0), the digital conversion results are the difference between the + and the - analog inputs selected by CS[0] (Table 4).
START and STOP Conditions The master initiates a transmission with a START (S) condition, a high-to-low transition on SDA while SCL is high. The master terminates a transmission with a STOP (P) condition, a low-to-high transition on SDA while SCL is high (Figure 5). A repeated START (Sr) condition can be used in place of a STOP condition to leave the bus active and the interface mode unchanged (see the HS Mode section). Acknowledge Bits Data transfers are acknowledged with an acknowledge bit (A) or a not-acknowledge bit (A). Both the master and the MAX11644/MAX11645 (slave) generate acknowledge bits. To generate an acknowledge, the receiving device must pull SDA low before the rising edge of the acknowledge-related clock pulse (ninth pulse) and keep it low during the high period of the clock pulse (Figure 6). To generate a not-acknowledge, the receiver allows SDA to be pulled high before the rising edge of the acknowledge-related clock pulse and leaves SDA high during the high period of the clock pulse. Monitoring the acknowledge bits allows for detection of unsuccessful data transfers. An unsuccessful data transfer happens if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master should reattempt communication at a later time.
S Sr P
Unipolar/Bipolar
When operating in differential mode, the BIP/UNI bit of the set-up byte (Table 1) selects unipolar or bipolar operation. Unipolar mode sets the differential input range from 0 to VREF. A negative differential analog input in unipolar mode causes the digital output code to be zero. Selecting bipolar mode sets the differential input range to VREF/2. The digital output code is binary in unipolar mode and two's complement in bipolar mode. See the Transfer Functions section. In single-ended mode, the MAX11644/MAX11645 always operate in unipolar mode irrespective of BIP/UNI. The analog inputs are internally referenced to GND with a full-scale input range from 0 to VREF.
2-Wire Digital Interface
The MAX11644/MAX11645 feature a 2-wire interface consisting of a serial-data line (SDA) and serial-clock line (SCL). SDA and SCL facilitate bidirectional communication between the MAX11644/MAX11645 and the master at rates up to 1.7MHz. The MAX11644/ MAX11645 are slaves that transfer and receive data. The master (typically a microcontroller) initiates data transfer on the bus and generates the SCL signal to permit that transfer. SDA and SCL must be pulled high. This is typically done with pullup resistors (750 or greater) (see the Typical Operating Circuit). Series resistors (RS) are optional. They protect the input architecture of the MAX11644/ MAX11645 from high voltage spikes on the bus lines and minimize crosstalk and undershoot of the bus signals.
SDA
SCL
Figure 5. START and STOP Conditions
S NOT-ACKNOWLEDGE
SDA ACKNOWLEDGE
Bit Transfer One data bit is transferred during each SCL clock cycle. A minimum of 18 clock cycles are required to transfer the data in or out of the MAX11644/MAX11645.
SCL
1
2
8
9
Figure 6. Acknowledge Bits
11
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2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 1-/2-Channel, 2-Wire Serial, 12-Bit ADCs MAX11644/MAX11645
Slave Address A bus master initiates communication with a slave device by issuing a START condition followed by a slave address. When idle, the MAX11644/MAX11645 continuously wait for a START condition followed by their slave address. When the MAX11644/MAX11645 recognize their slave address, they are ready to accept or send data. The slave address is factory programmed to 0110110. The least significant bit (LSB) of the address byte (R/W) determines whether the master is writing to or reading from the MAX11644/MAX11645 (R/W = 0 selects a write condition, R/W = 1 selects a read condition). After receiving the address, the MAX11644/MAX11645 (slave) issues an acknowledge by pulling SDA low for one clock cycle. Bus Timing At power-up, the MAX11644/MAX11645 bus timing is set for fast-mode (F/S mode), which allows conversion rates up to 22.2ksps. The MAX11644/MAX11645 must
operate in high-speed mode (HS mode) to achieve conversion rates up to 94.4ksps. Figure 1 shows the bus timing for the MAX11644/MAX11645's 2-wire interface.
HS Mode At power-up, the MAX11644/MAX11645 bus timing is set for F/S mode. The bus master selects HS mode by addressing all devices on the bus with the HS-mode master code 0000 1XXX (X = don't care). After successfully receiving the HS-mode master code, the MAX11644/MAX11645 issue a not-acknowledge, allowing SDA to be pulled high for one clock cycle (Figure 8). After the not-acknowledge, the MAX11644/ MAX11645 are in HS mode. The bus master must then send a repeated START followed by a slave address to initiate HS mode communication. If the master generates a STOP condition, the MAX11644/MAX11645 return to F/S mode.
MAX11644/MAX11645 S 0 1 1
SLAVE ADDRESS 0 1 1 0 R/W A
SDA
SCL
1
2
3
4
5
6
7
8
9
SEE ORDERING INFORMATION FOR SLAVE ADDRESS OPTIONS AND DETAILS.
Figure 7. MAX11644/MAX11645 Slave Address Byte
HS-MODE MASTER CODE S 0 0 0 0 1 X X X A Sr
SDA
SCL
F/S MODE
HS MODE
Figure 8. F/S-Mode to HS-Mode Transfer
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2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 1-/2-Channel, 2-Wire Serial, 12-Bit ADCs
Configuration/Setup Bytes (Write Cycle) A write cycle begins with the bus master issuing a START condition followed by seven address bits (Figure 7) and a write bit (R/W = 0). If the address byte is successfully received, the MAX11644/MAX11645 (slave) issues an acknowledge. The master then writes to the slave. The slave recognizes the received byte as the set-up byte (Table 1) if the most significant bit (MSB) is 1. If the MSB is 0, the slave recognizes that byte as the configuration byte (Table 2). The master
can write either one or two bytes to the slave in any order (setup byte, then configuration byte; configuration byte, then setup byte; setup byte or configuration byte only; Figure 9). If the slave receives a byte successfully, it issues an acknowledge. The master ends the write cycle by issuing a STOP condition or a repeated START condition. When operating in HS mode, a STOP condition returns the bus into F/S mode (see the HS Mode section).
MAX11644/MAX11645
MASTER TO SLAVE SLAVE TO MASTER A) ONE-BYTE WRITE CYCLE 1 S 7 SLAVE ADDRESS 11 WA 8 1 1 NUMBER OF BITS
SETUP OR A P OR Sr CONFIGURATION BYTE
MSB DETERMINES WHETHER SETUP OR CONFIGURATION BYTE B) TWO-BYTE WRITE CYCLE 1 S 7 SLAVE ADDRESS 11 WA 8 SETUP OR CONFIGURATION BYTE 1 A 8 1 1 NUMBER OF BITS
SETUP OR A P OR Sr CONFIGURATION BYTE
MSB DETERMINES WHETHER SETUP OR CONFIGURATION BYTE
Figure 9. Write Cycle
Table 1. Setup Byte Format
BIT 7 (MSB) REG BIT 7 6 5 4 3 2 1 0 BIT 6 SEL2 NAME REG SEL2 SEL1 SEL0 CLK BIP/UNI RST X 1 = external clock, 0 = internal clock. Defaults to 0 at power-up. 1 = bipolar, 0 = unipolar. Defaults to 0 at power-up (see the Unipolar/Bipolar section). 1 = no action, 0 = resets the configuration register to default. Setup register remains unchanged. Don't-care bit. This bit can be set to 1 or 0. Three bits select the reference voltage (Table 6). Default to 000 at power-up. BIT 5 SEL1 BIT 4 SEL0 BIT 3 CLK BIT 2 BIP/UNI BIT 1 RST BIT 0 (LSB) X
DESCRIPTION Register bit. 1 = setup byte, 0 = configuration byte (Table 2).
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13
2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 1-/2-Channel, 2-Wire Serial, 12-Bit ADCs MAX11644/MAX11645
Table 2. Configuration Byte Format
BIT 7 (MSB) REG BIT 7 6 5 4 3 2 1 0 BIT 6 SCAN1 NAME REG SCAN1 SCAN0 X X X CS0 SGL/DIF 1 = single-ended, 0 = differential (Tables 3 and 4). Defaults to 1 at power-up. See the SingleEnded/Differential Input section. Channel select bit. CS0 selects which analog input channels are to be used for conversion (Tables 3 and 4). Default to 0000 at power-up. BIT 5 SCAN0 BIT 4 X BIT 3 X DESCRIPTION Register bit. 1 = setup byte (see Table 1), 0 = configuration byte. Scan select bits. Two bits select the scanning configuration (Table 5). Default to 00 at power-up. BIT 2 X BIT 1 CS0 BIT 0 (LSB) SGL/DIF
X = Don't care.
Table 3. Channel Selection in Single-Ended Mode (SGL/DIF = 1)
CS0 0 1 AIN0 + + AIN1 GND -
Table 4. Channel Selection in Differential Mode (SGL/DIF = 0)
CS0 0 1 AIN0 + AIN1 +
14
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2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 1-/2-Channel, 2-Wire Serial, 12-Bit ADCs
Data Byte (Read Cycle) A read cycle must be initiated to obtain conversion results. Read cycles begin with the bus master issuing a START condition followed by seven address bits and a read bit (R/W = 1). If the address byte is successfully received, the MAX11644/MAX11645 (slave) issues an acknowledge. The master then reads from the slave. The result is transmitted in 2 bytes; first 4 bits of the first byte are high, then MSB through LSB are consecutively clocked out. After the master has received the byte(s), it can issue an acknowledge if it wants to continue reading or a not-acknowledge if it no longer wishes to read. If the MAX11644/MAX11645 receive a not-acknowledge, they release SDA, allowing the master to generate a STOP or a repeated START condition. See the Clock Modes and Scan Mode sections for detailed information on how data is obtained and converted. Clock Modes The clock mode determines the conversion clock and the data acquisition and conversion time. The clock mode also affects the scan mode. The state of the setup byte's CLK bit determines the clock mode (Table 1). At power-up, the MAX11644/MAX11645 are defaulted to internal clock mode (CLK = 0). Internal Clock When configured for internal clock mode (CLK = 0), the MAX11644/MAX11645 use their internal oscillator as the conversion clock. In internal clock mode, the MAX11644/MAX11645 begin tracking the analog input after a valid address on the eighth rising edge of the
clock. On the falling edge of the ninth clock, the analog signal is acquired and the conversion begins. While converting the analog input signal, the MAX11644/ MAX11645 hold SCL low (clock stretching). After the conversion completes, the results are stored in internal memory. If the scan mode is set for multiple conversions, they all happen in succession with each additional result stored in memory. The MAX11644/ MAX11645 contain two 12-bit blocks of memory. Once all conversions are complete, the MAX11644/ MAX11645 release SCL, allowing it to be pulled high. The master can now clock the results out of the memory in the same order the scan conversion has been done at a clock rate of up to 1.7MHz. SCL is stretched for a maximum of 8.3s per channel (see Figure 10). The device memory contains all of the conversion results when the MAX11644/MAX11645 release SCL. The converted results are read back in a first-in-first-out (FIFO) sequence. The memory contents can be read continuously. If reading continues past the result stored in memory, the pointer wraps around and points to the first result. Note that only the current conversion results are read from memory. The device must be addressed with a read command to obtain new conversion results. The internal clock mode's clock stretching quiets the SCL bus signal, reducing the system noise during conversion. Using the internal clock also frees the bus master (typically a microcontroller) from the burden of running the conversion clock, allowing it to perform other tasks that do not need to use the bus.
MAX11644/MAX11645
MASTER TO SLAVE SLAVE TO MASTER
A) SINGLE CONVERSION WITH INTERNAL CLOCK 1 S 7 SLAVE ADDRESS tACQ tCONV 11 RA CLOCK STRETCH 8 RESULT 4 MSBs A 8 RESULT 8 LSBs 1 1 NUMBER OF BITS
A P OR Sr
B) SCAN MODE CONVERSIONS WITH INTERNAL CLOCK 1 S 7 SLAVE ADDRESS tACQ1 tCONV1 11 RA CLOCK STRETCH CLOCK STRETCH 8 1 8 1 8 1 8 1 1 NUMBER OF BITS
RESULT 1 ( 4MSBs) A RESULT 1 (8 LSBs) A
RESULT N (4MSBs) A RESULT N (8LSBs) A P OR Sr
tACQ2 tCONV2
tACQN tCONVN
Figure 10. Internal Clock Mode Read Cycles
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15
2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 1-/2-Channel, 2-Wire Serial, 12-Bit ADCs MAX11644/MAX11645
External Clock When configured for external clock mode (CLK = 1), the MAX11644/MAX11645 use the SCL as the conversion clock. In external clock mode, the MAX11644/ MAX11645 begin tracking the analog input on the ninth rising clock edge of a valid slave address byte. Two SCL clock cycles later, the analog signal is acquired and the conversion begins. Unlike the internal clock mode, converted data is available immediately after the first four empty high bits. The device continuously converts input channels dictated by the scan mode until given a not-acknowledge. There is no need to readdress the device with a read command to obtain new conversion results (see Figure 11). The conversion must complete in 1ms, or droop on the track-and-hold capacitor degrades conversion results.
Use internal clock mode if the SCL clock period exceeds 60s. The MAX11644/MAX11645 must operate in external clock mode for conversion rates from 40ksps to 94.4ksps. Below 40ksps, internal clock mode is recommended due to much smaller power consumption.
Scan Mode SCAN0 and SCAN1 of the configuration byte set the scan mode configuration. Table 5 shows the scanning configurations. The scanned results are written to memory in the same order as the conversion. Read the results from memory in the order they were converted. Each result needs a 2-byte transmission; the first byte begins with 4 empty bits, during which SDA is left high. Each byte has to be acknowledged by the master or the memory transmission is terminated. It is not possible to read the memory independently of conversion.
MASTER TO SLAVE SLAVE TO MASTER
A) SINGLE CONVERSION WITH EXTERNAL CLOCK 1 S 7 SLAVE ADDRESS 11 RA 8 RESULT (4 MSBs) tACQ tCONV 1 A 8 RESULT (8 LSBs) 1 A 1 P OR Sr NUMBER OF BITS
B) SCAN MODE CONVERSIONS WITH EXTERNAL CLOCK 1 S 7 SLAVE ADDRESS 11 RA 8 RESULT 1 (4 MSBs) tACQ1 tCONV1 1 A 8 RESULT 2 (8 LSBs) 1 A tACQ2 8 RESULT N (4 MSBs) tACQN tCONVN 1 A 8 RESULT N (8 LSBs) 1 1 NUMBER OF BITS
A P OR Sr
Figure 11. External Clock Mode Read Cycle
Table 5. Scanning Configuration
SCAN1 0 0 1 1 SCAN0 0 1 0 1 SCANNING CONFIGURATION Scans up from AIN0 to the input selected by CS0. Converts the input selected by CS0 eight times (see Tables 3 and 4).* Reserved. Do not use. Converts the input selected by CS0.*
*When operating in external clock mode, there is no difference between SCAN[1:0] = 01 and SCAN[1:0] = 11, and converting occurs perpetually until not-acknowledge occurs.
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2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 1-/2-Channel, 2-Wire Serial, 12-Bit ADCs MAX11644/MAX11645
Table 6. Reference Voltage and REF Format
SEL2 0 0 1 1 1 1 SEL1 0 1 0 0 1 1 SEL0 X X 0 1 0 1 REFERENCE VOLTAGE VDD External reference Internal reference Internal reference Internal reference Internal reference REF Not connected Reference input Not connected* Not connected* Reference output Reference output INTERNAL REFERENCE STATE Always off Always off Always off Always on Always off Always on
X = Don't care. *Preferred configuration for internal reference.
Applications Information
Power-On Reset
The configuration and setup registers (Tables 1 and 2) default to a single-ended, unipolar, single-channel conversion on AIN0 using the internal clock with VDD as the reference. The memory contents are unknown after power-up.
Automatic Shutdown Automatic shutdown occurs between conversions when the MAX11644/MAX11645 are idle. All analog circuits participate in automatic shutdown except the internal reference due to its prohibitively long wake-up time. When operating in external clock mode, a STOP, notacknowledge, or repeated START condition must be issued to place the devices in idle mode and benefit from automatic shutdown. A STOP condition is not necessary in internal clock mode to benefit from automatic shutdown because power-down occurs once all conversion results are written to memory (Figure 10). When using an external reference or VDD as a reference, all analog circuitry is inactive in shutdown and supply current is less than 0.5A. The digital conversion results obtained in internal clock mode are maintained in memory during shutdown and are available for access through the serial interface at any time prior to a STOP or a repeated START condition. When idle, the MAX11644/MAX11645 continuously wait for a START condition followed by their slave address (see the Slave Address section). Upon reading a valid address byte, the MAX11644/MAX11645 power up. The internal reference requires 10ms to wake up, so when using the internal reference it should be powered up 10ms prior to conversion or powered continuously. Wake-up is invisible when using an external reference or VDD as the reference.
Automatic shutdown results in dramatic power savings, particularly at slow conversion rates and with internal clock. For example, at a conversion rate of 10ksps, the average supply current for the MAX11645 is 60A (typ) and drops to 6A (typ) at 1ksps. At 0.1ksps the average supply current is just 1A, or a minuscule 3W of power consumption. See Average Supply Current vs. Conversion Rate (External Clock) in the Typical Operating Characteristics section).
Reference Voltage
SEL[2:0] of the setup byte (Table 1) control the reference configuration (Table 6).
Internal Reference The internal reference is 4.096V for the MAX11644 and 2.048V for the MAX11645. When REF is configured to be an internal reference output (SEL[2:1] = 11), decouple REF to GND with a 0.1F capacitor and a 2k series resistor (see the Typical Operating Circuit). Once powered up, the reference always remains on until reconfigured. The internal reference requires 10ms to wake up and is accessed using SEL0 (Table 6). When in shutdown, the internal reference output is in a highimpedance state. The reference should not be used to supply current for external circuitry. The internal reference does not require an external bypass capacitor and works best when left unconnected (SEL1 = 0). External Reference The external reference can range from 1V to VDD. For maximum conversion accuracy, the reference must be able to deliver up to 40A and have an output impedance of 500k or less. If the reference has a higher output impedance or is noisy, bypass it to GND as close as possible to REF with a 0.1F capacitor.
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17
2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 1-/2-Channel, 2-Wire Serial, 12-Bit ADCs MAX11644/MAX11645
Transfer Functions
Output data coding for the MAX11644/MAX11645 is binary in unipolar mode and two's complement in bipolar mode with 1 LSB = (VREF/2N) where N is the number of bits (12). Code transitions occur halfway between successive-integer LSB values. Figures 12 and 13 show the input/output (I/O) transfer functions for unipolar and bipolar operations, respectively. Minimize capacitor lead length for best supply noise rejection, and add an attenuation resistor (5) in series with the power supply if it is extremely noisy.
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best straight-line fit or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. The MAX11644/MAX11645's INL is measured using the endpoint.
Layout, Grounding, and Bypassing
Only use PCBs. Wire-wrap configurations are not recommended since the layout should ensure proper separation of analog and digital traces. Do not run analog and digital lines parallel to each other, and do not layout digital signal paths underneath the ADC package. Use separate analog and digital PCB ground sections with only one star point (Figure 14) connecting the two ground systems (analog and digital). For lowest noise operation, ensure the ground return to the star ground's power supply is low impedance and as short as possible. Route digital signals far away from sensitive analog and reference inputs. High-frequency noise in the power supply (VDD) could influence the proper operation of the ADC's fast comparator. Bypass VDD to the star ground with a network of two parallel capacitors, 0.1F and 4.7F, located as close as possible to the MAX11644/MAX11645 power-supply pin.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of less than 1 LSB guarantees no missing codes and a monotonic transfer function.
Aperture Jitter
Aperture jitter (tAJ) is the sample-to-sample variation in the time between the samples.
Aperture Delay
Aperture delay (tAD) is the time between the falling edge of the sampling clock and the instant when an actual sample is taken.
OUTPUT CODE FULL-SCALE TRANSITION
OUTPUT CODE
MAX11644 MAX11645
11 . . . 111 11 . . . 110 11 . . . 101
011 . . . 111 011 . . . 110
V FS = REF 2 ZS = 0 -VREF 2 VREF 1 LSB = 4096 -FS =
MAX11644 MAX11645
000 . . . 010 000 . . . 001
FS = VREF ZS = GND V 1 LSB = REF 4096
000 . . . 000 111 . . . 111 111 . . . 110 111 . . . 101
00 . . . 011 00 . . . 010 00 . . . 001 00 . . . 000 0 1 2 3 INPUT VOLTAGE (LSB)
100 . . . 001 100 . . . 000
FS
- FS
FS - 3/2 LSB
0 INPUT VOLTAGE (LSB)
+FS - 1 LSB
Figure 12. Unipolar Transfer Function
Figure 13. Bipolar Transfer Function
18
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2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 1-/2-Channel, 2-Wire Serial, 12-Bit ADCs
Signal-to-Noise Plus Distortion
SUPPLIES GND
MAX11644/MAX11645
Signal-to-noise plus distortion (SINAD) is the ratio of the fundamental input frequency's RMS amplitude to the RMS equivalent of all other ADC output signals.
VLOGIC = 3V/5V
3V OR 5V
SignalRMS SINAD(dB) = 20 x log NoiseRMS + THDRMS
R* = 5
4.7F
Effective Number of Bits
Effective number of bits (ENOB) indicates the global accuracy of an ADC at a specific input frequency and sampling rate. An ideal ADC's error consists of quantization noise only. With an input range equal to the ADC's full-scale range, calculate the ENOB as follows: ENOB = (SINAD - 1.76)/6.02
0.1F VDD GND 3V/5V DGND
MAX11644 MAX11645
DIGITAL CIRCUITRY
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS sum of the input signal's first five harmonics to the fundamental itself. This is expressed as: 2 V + V32 + V42 + V52 THD = 20 x log 2 V1 where V1 is the fundamental amplitude, and V2 through V5 are the amplitudes of the 2nd- through 5th-order harmonics.
*OPTIONAL
Figure 14. Power-Supply Grounding Connection
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC's resolution (N bits): SNRMAX[dB] = 6.02dB x N + 1.76dB In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first five harmonics, and the DC offset.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest distortion component.
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19
2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 1-/2-Channel, 2-Wire Serial, 12-Bit ADCs MAX11644/MAX11645
Typical Operating Circuit
3.3V or 5V
Selector Guide
PART INTERNAL SUPPLY INPUT INL REFERENCE VOLTAGE CHANNELS (LSB) (V) (V) 2 singleended/1 differential 2 singleended/1 differential
0.1F VDD ANALOG INPUTS AIN0 AIN1 MAX11644 MAX11645 RS* SDA SCL RS * REF GND 5V 5V RP C SDA SCL RP
MAX11644
4.096
4.5 to 5.5
1
RC NETWORK* 2k CREF 0.1F
MAX11645
2.048
2.7 to 3.6
1
*OPTIONAL
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE 8 MAX PACKAGE CODE U8CN+1 DOCUMENT NO. 21-0036
20
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2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 1-/2-Channel, 2-Wire Serial, 12-Bit ADCs
Revision History
REVISION NUMBER 0 REVISION DATE 4/10 Initial release DESCRIPTION PAGES CHANGED --
MAX11644/MAX11645
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 21
(c) 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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